1. Field of the Invention
This invention generally relates to integrated circuits; and more specifically, the invention relates to a design structure for in-system repair of memory arrays on integrated circuits.
2. Background Art
Integrated circuits typically contain memory arrays. Memory arrays can be classified as non-redundant or redundant. Redundant arrays have spare wordlines and/or bitlines. In the event of detection of a fail in the array during manufacturing test, the redundant wordlines or bitlines can be substituted for failing wordlines or bitlines. The information that encodes the use of redundant elements for any particular memory array can be stored—for example as described in U.S. Pat. No. 6,577,156—in a set of fuses located remotely from the memory arrays themselves.
According to the procedure disclosed in U.S. Pat. No. 6,577,156, when the integrated circuit is powered-on, the fuse information is decoded and transferred to the memory arrays using a serial scan chain, thereby enabling the required redundant word and/or bitlines in the memory arrays. At the conclusion of this procedure, the memory array operates as if it were manufactured perfectly. Any subsequent memory tests are supposed to pass.
However, if the memory array develops a new failure in the field, the above-discussed procedure is not effective for fixing that fail.